The present invention relates to a memory device, and more particularly to a monolithic semiconductor memory device formed on a semiconductor substrate.
As is well known, memory devices are generally classified, with respect to the mode of access, into the so-called random access memories and the so-called serial access memories. The random access memory is constructed in such manner that memory cells are arrayed in a matrix form and peripheral circuits such as address inverters and decoders are disposed along the periphery of the matrix. In such type of random access memory, since each memory cell is formed of one transistor and one capacitor, a memory matrix having a large memory capacity can be constructed at a high density. However, contrary to the tendency of high-density integration of a memory cell matrix, in a peripheral circuit such as a decoder, the number of input transistors of a NOR gate corresponding to one word line or one digit line, is increased in proportion to the enlargement of memory capacity of the memory matrix. In other words, the number of elements necessitated for a peripheral circuit per one word line or one digit line is rapidly increased in accordance with the increase in a memory capacity. Consequently, the proportion of the area occupied by memory cells on a semiconductor chip is greatly restricted, and hence it has been difficult in the prior art to provide a memory device having a large memory capacity with a small chip area.
On the other hand, among the serial access memories, a shift register has been well known as a typical example. In the case of the shift register, although a peripheral circuit such as a decoder or the like is unnecessary, a memory unit of one bit is constructed by cascading two stages of inverters each provided with a sampling gate transistor. Accordingly, at least six transistors per one bit are necessary, and hence, in the event of a large memory capacity, a great many transistors are necessitated. In other words, realization of a serial access memory having a large memory capacity has been not practicable in the prior art.
For instance, a shift register employing MOS FET's is a most common one, and substantially every semiconductor manufacturer in the world has developed and sold various shift registers. The number of bits in such a shift register was fixed at the time point when it was designed and completed. In the event that different shift lengths of the shift register were required depending upon the use, one had to fulfill such a requirement by preparing a plurality of shift registers having different shift-lengths. However, as the number of systems making use of shift registers is increased, it has become difficult to fulfill all these requirements. Hence this problem has been dealt with by standardizing the lengths of the available shift registers on the side of the system designers.
Nevertheless, in some systems, a requirement has arisen that the length of a shift register should not be fixed, but it is desired to control the shift-length of the shift register depending upon the situation.
In the field of audio equipments which handle analog signals, a delay circuit has been used in an echo device or the like, and it was desired to provide an echo device in which the length of an echo can be freely controlled. Heretofore, in one method for making a delay time of an analog signal variable, an analog delay circuit, for example a BBD (Bucket Brigade Device) was employed and the delay time was controlled by varying a sampling period. However, in the system of varying a sampling period, the width of the delay control was limited, and also the variation of the sampling period affected the precision of the signal.
In addition, recently, with the progress of the technique of digitally processing a signal, especially an analog signal, as is the case with a digital filter, the necessity for a large-capacity memory device, especially a large-capacity serial access memory has been enhanced.